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Driving Freescale SERDES Clocks with IDT PCIe Devices
PCI Express (PCIe) Clock Overview by IDT
PCI Express (PCIe) Clock Multiplexers by IDT
PCI Express Common Clock Jitter Model and Transfer Functions
Overview of Timing Requirements for NXP QorIQ LS Processors
PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview
IDT Timing Solutions for NXP QorIQ / Layerscape CPU
Programmable Clock Generator with PCIe Timing Outputs by IDT
Understanding SRIS in PCIe Systems | Synopsys
Choosing the PLL Bandwidth for Zero Delay Buffers in PCIe Timing Systems
IDT ClockMatrix™ 8A3404x Multi-channel DPLL / DCO Programmable, Sub-150fs Jitter Timing Solution
Standard HCSL vs. Low-Power HCSL (LP-HCSL) Output Signaling
